This invention relates to signal encoders/decoders, and in particular to A/D (analogue to digital) converters and to devices such as flux reference stores therefor.
A typical successive approximation A/D converter is illustrated in FIG. 1 of the accompanying drawings. It comprises an input 1, a sample and hold 2, a comparator 3, a successive approximation register 4, which itself comprises a digital register and control circuits therefor, and an n-bit D/A converter 5, and produces a n-bit parallel digital output as indicated. The converter of FIG. 1 basically operates as follows, namely: an input analogue signal sample, for example, voltage, current or some other parameter, is taken by the sample and hold 2 and this sample is successively classified to the nearest 1/2, 1/4, 1/8, 1/16 etc. of a maximum intended "full scale" value, to determine the digital equivalent. The numbers in the digital register of the register 4 are initially all set to zero by means of the control circuits. Then the control circuits set the highest order digit to "1", the resulting digital number is converted to an analogue value in the converter 5 and is compared with the sampled input value at the comparator 3. If the input value is equal to or larger than the converted value the register digit is left at "1", otherwise it is reset to "0". Then the next highest digit is set to "1", the resulting digital number converted to an analogue value and compared with the input value sample, and so on. At the conclusion the digital representation of the analogue value is stored in the register and may be transmitted from the register in parallel form.
A limit to the production of high-speed high-accuracy A/D converters is the need for a range of precision references (resistances) in the D/A converter 5 used in the successive approximation loop. Furthermore, a high accuracy comparator is needed.